1. Field of the Invention
The present invention relates to the field of testing dynamic logic and related logic families such as N-Nary logic. More specifically, the present invention relates to scan testing of dynamic logic and N-Nary logic using on-chip circuitry.
2. Description of the Related Art
The increasing complexity of integrated circuits, often containing millions of transistors, has created a need for sophisticated test methodologies to insure functionality at multiple levels. Semiconductors must undergo some degree of functional testing before they are shipped to computer and other device manufacturers, and they must be periodically tested during further manufacturing and during their operating life to verify continuing operability. One of the problems encountered in testing is the difficulty in accessing and isolating circuits that are deeply embedded in the chip.
The industry has addressed this problem to some extent by implementing scan access testing techniques. Scan access refers broadly to the use of specialized serial shift registers (xe2x80x9cscan registersxe2x80x9d) to deliver stimulus vectors from a stimulus pattern generator to circuit nodes of interest, and to retrieve response data from circuit nodes of interest for analysis. Scan registers function as normal synchronous registers and latch data propagating through the computational logic. However, scan registers can also be interconnected in such a way as to allow propagation of data directly from register to register upon assertion of control signals or clocks, thereby bypassing any computation logic between the registers. This provides a means whereby stimulus data may be transported directly to internal circuit nodes without propagating through computational logic, and whereby response data may be retrieved directly from internal circuit nodes without propagating through computational logic, thus allowing designers to isolate sections of logic for testing.
The benefit of scan access increases as the proportion of circuit nodes otherwise inaccessible from primary inputs and outputs increases. xe2x80x9cFull scanxe2x80x9d refers to an implementation of scan access wherein every register on a chip is accessible through scan. xe2x80x9cPartial scanxe2x80x9d refers to an implementation of scan access wherein some subset of the registers on a chip are accessible through scan.
Conventional scan access, i.e., propagating data through a long chain of interconnected scan registers, is inherently serial in nature. The number of clock cycles needed to load or unload the scan chain is equal to the number of registers in the chain. Gaining access to internal nodes is therefore accomplished only at the cost of very long test times.
Alternate scan architectures such as random access scan have been used to remedy the test time problem caused by the serial nature of scan access. Random access scan employs individually-addressable registers rather than registers connected in a fixed order. This adds greater flexibility to the order in which registers may be accessed, but reduces overall test time only when writing or reading some subset of the registers. Random access scan does not decrease the total number of clock cycles needed to write or read all registers.
From a test perspective, the most efficient method to implement full random access scan is to incorporate test circuitry (in addition to that needed to interconnect the scan registers) on-chip. Placing circuitry on chip eliminates the need to develop specialized test hardware, and potentially enables desirable test options such as testing of the chip under special clock conditions, or in situ following the integration into a system-level product.
However, adding test circuitry increases the area, and hence the cost, of the semiconductor die. When test circuitry is incorporated into a semiconductor, the benefit gained by increased test coverage must be traded off against the increased die area and associated cost. Moreover, the test circuitry must not interfere with the normal operation of the chip. Because of these constraints, the ratio of circuitry under test to test circuitry in current semiconductors is relatively high. Consequently, typical on-chip random access scan implementations control and observe only the primary inputs and outputs of relatively large blocks of logic. Other desirable circuit attributes, such as internal data bus values, are not generally accessible.
Moreover, while random-access scan using on-chip circuitry does significantly improve manufacturing testability, designers have been thus far unable to capitalize on its potential to a facilitate chip debug during the design process. In general, most test points on a chip can only be scanned when the chip is in a xe2x80x9cscan mode,xe2x80x9d meaning that the clocks are stopped or slowed significantly, the machine is given a set of input test vectors which propagate through the logic, and outputs are then scanned and analyzed to determine whether the logic is operating properly. Thus, when a chip is in scan mode the information in a scan register is somewhat artificial, in that it did not arrive under normal operating conditions, and it is the result of a test vector rather than a real application running on the processor.
Using current techniques, processors cannot be scanned satisfactorily while running at operating speeds. A processor""s clocks cannot be stopped abruptly to read a test point without causing a voltage overload in the supply network due to the very high di/dt. This limitation means that designers generally have no visibility into what is happening internally in real time, which significantly hampers troubleshooting and debugging performance-related problems. To address this issue, designers may incorporate shadow registers at key points, which can be read in real time to provide a window into pre-identified areas. However, this solution is less than ideal, particularly for highly complex designs, in that it requires up-front identification of points of interest. Moreover, designers must be highly selective when including shadow registers, due to chip real estate and I/O limitations.
The present invention is an improved scan approach that utilizes a RAM-like scan bus architecture to provide visibility into even deeply embedded logic within a chip. While the present invention can be applied to implement scan in any dynamic logic design, the advantages of the present invention are best realized in a design wherein the logic is synchronized using multiple clock domains with overlapping phases, as described in the Logic Synchronization Patent. In designs that employ this logic synchronization method, the present invention allows the processor to be stopped, information to be accessed or provided, processor state to be modified, and operation to be resumed, all without corrupting the machine""s architectural state. In addition, the present invention is capable of xe2x80x9cfreezingxe2x80x9d certain gates for scanning when the processor is running at operating or near-operating speed, without the use of shadow registers.
This disclosure describes the present invention in the context of a new dynamic logic family called N-Nary logic, which itself is more fully described in a copending patent application, U.S. Pat. App. Ser. No. 09/019355, filed Feb. 5, 1998, now U.S. Pat. No. 6,066,965 and titled xe2x80x9cMethod and Apparatus for a N-Nary logic Circuit Using 1-of-4 Encodingxe2x80x9d (referred to herein as xe2x80x9cThe N-Nary Patent.xe2x80x9d). The N-Nary patent is incorporated by reference for all purposes. Those skilled in the art will understand, after reading this specification or practicing the present invention, that the present invention can be implemented in other applications that employ other logic design methodologies.
Finally, this application is also related to the following U.S. Patent Applications:
These five patent applications are hereby incorporated by reference for all purposes into this specification.
The present invention comprises a method and apparatus for random-access scan of a network of dynamic logic or N-nary logic, wherein the network includes sequentially clocked precharge logic gates and one or more scan gates. Each clocked precharge logic gate and each scan gate further comprise a logic tree having one or more evaluate nodes, a precharge circuit, an evaluate circuit, and one or more output buffers. Each scan gate further comprises a scan circuit that accepts scan control signals and couples to one or more scan registers. A scan control circuit generates scan control signals and scan timing signals which operate to capture the state of the output buffers of the scan gate and provide that state to one or more scan registers. Scan control signals and scan timing signals also operate to force the output buffers of the scan gate to a preselected level, which then propagates through the network to create an output state on the next scan gate in the network, which can then be read and compared to an expected output state given the output state of the previous scan gate.